As semiconductor integrated circuit devices (hereinafter called simply “flip-chip semiconductor integrated circuit devices”) wherein protruded electrodes such as solder bumps or the like are formed, there are known Unexamined Patent Publication No. Hei 5(1993)-218042, Unexamined Patent Publication No. Hei 8(1996)-250498, and U.S. Pat. No. 5,547,740. Each of these Publications shows one basic form of the flip-chip semiconductor integrated circuit device.
In the flip-chip semiconductor integrated circuit device described in each of the above Publications, rewirings are routed from bonding pads of a chip thereof, for example, and bump electrodes connected to the rewirings are placed on the surface of the chip in an array (area array) form. The bump electrodes disposed in such an area array form are exposed from a surface protective film. It is thus possible to enlarge the interval between the adjacent bump electrodes and facilitate the board packaging that bump electrodes are connected to wirings on a printed circuit board. Further, a low-cost printed circuit board wide in wiring interval can be utilized. In such a flip-chip semiconductor integrated circuit device, the bump electrodes are terminals directly connected to the printed circuit board. Only the bump electrodes are exposed and the bonding pads of the semiconductor chip are covered with an insulating film or a protective film. Therefore, the bump electrodes correspond to external connecting terminals such as lead pins of a package such as a QFP or the like.
In the above-described flip-chip semiconductor integrated circuit device, there is a tendency to more and more increase the scale of each internal circuit for the purpose of improvements in function. Whilst the size of one semiconductor chip is made large with the increase in circuit scale, a circuit's wiring width becomes small. Therefore, for example, in a clock-operated semiconductor integrated circuit device, a signal delay is developed while a clock supplied from an external terminal is being transmitted through an internal wiring. A skew occurs between clocks supplied to individual internal circuits and a timing margin for accommodating it is required, thus interfering with the transition of the clock to a high frequency. A problem arises in that when a source voltage is stepped down in association with low power consumption, device micro-fabrication, etc. and set as an operating voltage for each internal circuit, it is necessary to provide a plurality of step down voltage generators for the purpose of preventing a voltage loss in the internal wiring, and hence current consumption at such step down circuit units will increase and a circuit scale will increase.
An object of the present invention is to provide a semiconductor integrated circuit device capable of speeding up its operation and enabling circuit's rational arrangements. Another object of the present invention is to provide a semiconductor integrated circuit device capable of enhancing the degree of freedom of the layout of circuits lying within a chip in a simple configuration. The above, other objects, and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.